The present invention relates to a process for fabricating a semiconductor device in which a trench is formed at the surface of a silicon substrate, a capacitor is formed at the trench, and element isolation is also achieved at the trench.
An example of a prior art process of this nature is disclosed in Japanese Patent Application Publication No. 12739/1983. This prior art is described with reference to FIGS. 1A to 1D.
First, as shown in FIG. 1A, an oxide mask 2 for forming a trench is formed on a semiconductor substrate 1.
Next, a reactive ion etching (RIE) is performed using the oxide mask 2 as a mask to form a trench 3, as shown in FIG. 1B.
Then, the oxide mask 2 is removed, and an insulator film 4 is formed as shown in FIG. 1C.
Polysilicon 5 is thereafter formed in the trench 3 covered with the insulator film 4. The polysilicon 5 acts as a capacitor electrode.
The above process has a drawback in that the trench formed by the reactive ion etching has sharp edges. This tendency is more acute in the formation of the minute patterns required today. The sharp edges can cause a concentrated electric field and stress in the insulator film formed thereon. As a result, leakage currents may occur. This can deteriorate the device characteristic or make the device inoperative. As a solution to this problem, attempts have been made to slightly etch the substrate surface after removal of the oxide film, or to form a thin oxide film and then remove it. But they have not been successful.